Bi-directional power switch

ABSTRACT

A semiconductor device that is comprised to two or more MOSFETs to form a bi-directional power switch. One embodiment of the bi-directional switch is comprised of (a) a semiconductor substrate having an upper surface and a lower surface; (b) a first region of a first conductivity type in said semiconductor substrate and proximate to said upper surface; (c) a first source region and a second source region of a second conductivity type within said first region; (d) a drain region of a second conductivity type formed within said first region and proximate to said upper surface and between said first and second source regions; (e) a first source overlaying and connecting said first source region; (f) a second source overlaying and connecting said second source region; (g) a first gate above said upper surface and placed between said first source and said second source wherein said first gate overlays a portion of said first source region and said drain region; (h) a second gate above said upper surface and placed between said second source and said first gate wherein said second gate overlays a portion of said second source region and said drain region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application60/444,943, filed Feb. 4, 2003 and U.S. Provisional Application60/501,192, filed Sep. 8, 2003, each of which are hereby incorporated byreference in its entirety.

BACKGROUND OF THE INVENTION

I. Field of the Invention

The present invention generally relates to the field of semiconductordevices and more particularly to bi-directional power switches.

2. Related Background Art

Power MOSFETs (metal-oxide-semiconductor field-effect transistor) areused to create monolithic bi-directional power switches (“BDS”).Bi-directional switches are used in many applications, such as inbattery charging circuitry to permit controlling the discharging andcharging of batteries. For instance, lithium-ion batteries should notcontinue to be charged after they are fully charged to prevent dangerousand catastrophic failures and fires.

Two types of bi-directional switches are currently available. The firsttype is exemplified by products such as Siliconix's Si8900EDB andInternational Rectifier's FlipFET. In these types of switches, thedrains of two MOSFETs are connected together through a common siliconsubstrate as shown in FIG. 2. The second type is exemplified by productssuch as Fairchild's FDZ2551N where the drains are connected through anexpensive copper package.

In both cases, current flow for these MOSFETs goes from the source tothe drain via the substrate. When creating bi-directional switches, twovertical trench MOSFETS are used and connected via a common drain. Thefirst type of bi-directional switch (e.g. Siliconix's Si8900EDB andInternational Rectifier's FlipFET) have higher R_(DSON) (staticdrain-source on-resistance). This is because using vertical trenchMOSFETs creates long current pathways from the source of the firstMOSFET to the source of the second MOSFET. In particular, current firsttravels down vertically, then horizontally through the substrate thenback up vertically. This causes the current to travel through highresistance structures resulting in, inter alia, high R_(DSON) values.The second type has a lower R_(DSON) but a high cost due to theadditional copper package.

Accordingly, there is a need to provide bi-directional power switcheswith efficient current flow and without the need for costly packaging.There is also a need for bi-directional switches with improved (i.e.,lower) on-resistance and monolithic structures.

BRIEF SUMMARY OF THE INVENTION

According to an embodiment of the present invention, a lateral MOSFETbi-directional switch is disclosed. In accordance with one aspect of thepresent invention, a semiconductor device is disclosed with (a) asemiconductor substrate having an upper surface and a lower surface; (b)a first region of a first conductivity type in said semiconductorsubstrate and proximate to said upper surface; (c) a first source regionand a second source region of a second conductivity type within saidfirst region; (d) a drain region of a second conductivity type formedwithin said first region and proximate to said upper surface and betweensaid first and second source regions; (e) a first source overlaying andconnecting said first source region; (f) a second source overlaying andconnecting said second source region; (g) a first gate above said uppersurface and placed between said first source and said second sourcewherein said first gate overlays a portion of said first source regionand said drain region; (h) a second gate above said upper surface andplaced between said second source and said first gate wherein saidsecond gate overlays a portion of said second source region and saiddrain region.

In accordance with another aspect of the present invention, asemiconductor device is disclosed with (a) a semiconductor substratehaving an upper surface and a lower surface; (b) a first region of afirst conductivity type in said semiconductor substrate and proximate tosaid upper surface; (c) a second region and a third region of a secondconductivity type within said first well region; (d) a first sourceregion of a first conductivity type within said second region and asecond source region having a first conductivity type within said thirdregion; (e) a first source overlaying and connecting said first sourceregion; (f) a second source overlaying and connecting said second sourceregion; (g) a first gate above said upper surface and placed betweensaid first source and said second source wherein said first gateoverlays a portion of said first source region and said second region;(h) a second gate above said upper surface and placed between saidsecond source and said first gate wherein said second gate overlays aportion of said second source region and said third region.

In accordance with yet another aspect of the present invention, asemiconductor device is disclosed with (a) a semiconductor substratehaving an upper surface and a lower surface; (b) a first region and asecond region of a first conductivity type in said semiconductorsubstrate and proximate to said upper surface; (c) a first connectingregion within said first region of a first conductivity type and a firstsource region within said first region of a second conductivity type;(d) a second connecting region within said second region of a firstconductivity type and a second source region within said second regionof a second conductivity type; (e) a first source overlaying andconnecting said first source region; (f) a second source overlaying andconnecting said second source region; (g) a first gate above said uppersurface and placed between said first source and said second sourcewherein said first gate overlays a portion of said first source regionand said first region; (h) a second gate above said upper surface andplaced between said second source and said first gate wherein saidsecond gate overlays a portion of said second source region and saidsecond region.

In accordance with yet another aspect of the present invention, asemiconductor device is disclosed with (a) a semiconductor substratehaving an upper surface and a lower surface; (b) a first region of afirst conductivity type proximate to said upper surface; (c) a pluralityof second regions of a second conductivity type within said first wellregion, each of said second region having a first source region of afirst conductivity type within said second regions; (d) a plurality ofthird regions of a second conductivity type within said first region,each of said third region having a second source region of a firstconductivity type within said third region; (e) a plurality of firstsources overlaying and connecting said plurality of said first sourceregions; (f) a plurality of second sources overlaying and connectingsaid plurality of said second source regions; (g) a plurality of firstgates above said upper surface wherein each first gate is placed betweena first source and a second source and overlays a portion of said firstsource region and said second region; (h) a plurality of second gatesabove said upper surface wherein each second gate is placed between asecond source and first gate and overlays a portion of said secondsource region and said third region.

In accordance with yet another aspect of the present invention asemiconductor device is disclosed having a plurality of first sourcesand a plurality of second sources wherein current flows from a firstsource to an associated second source. The semiconductor device have thefirst sources dispersed among the second sources. The semiconductordevide may also have current paths from different first sources toassociated second sources that are substantially similar.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an exemplary application of bi-directional switches.

FIG. 2 is a prior art trench MOSFET bi-directional switch.

FIG. 3 is a cross sectional view of a MOSFET in accordance with anembodiment of the present invention.

FIG. 4 is a cross sectional view of a MOSFET in accordance with anotherembodiment of the present invention.

FIG. 5 a is a cross sectional view of one cell of a bi-directionalswitch in accordance with an embodiment of the present invention.

FIG. 5 b is a top view one embodiment of FIG. 5 a.

FIG. 5 c is a cross sectional view of one cell of a bi-directionalswitch in accordance with an embodiment of the present invention.

FIG. 6 a cross sectional view of one cell of a bi-directional switch inaccordance with an embodiment of the present invention.

FIG. 7 is a cross sectional view of a bi-directional switch composed ofmultiple cells.

FIG. 8 is a cross sectional view of a bi-directional switch usingmultiple cells and conventional technology in accordance with anembodiment of the present invention.

FIG. 9 a is a top view of solder bumps of an exemplary device withoutaccess to the drain.

FIG. 9 b is a top view of solder bumps of an exemplary device withaccess to the drain.

It will be appreciated that for simplicity and clarity of illustration,elements illustrated in the figures have not necessarily been drawn toscale. For example, the dimensions of some of the elements areexaggerated relative to other elements for clarity. Further, whereconsidered appropriate, reference numerals have been repeated among thefigures to indicate corresponding or analogous elements.

DESCRIPTION OF THE INVENTION

The preferred embodiment of the present invention uses conventional CMOSfabrication processes to fabricate a semiconductor device embodying thepresent invention to reduce the costs of production. In accordance withone aspect of the present invention, however, only one type of MOSFETs(either an n-channel or p-channel MOSFET) is made on the die. Since thedevice of the present invention only consists of parallel n-channel orp-channel transistors, the problem of latch-up is avoided.

In one embodiment, multiple bi-directional switches are fabricated on asingle monolithic chip and connected in parallel. Preferably, thesebi-directional switches are interconnected by runners that are short andwide. These interconnections are disclosed in more detail in U.S. patentapplication Ser. No. 10/601,121 filed Jun. 19, 2003 and U.S. ProvisionalApplication 60/416,942 filed Oct. 8, 2002, both incorporated herein byreference in their entirety.

Referring now to FIG. 1, there is shown an exemplary application for thepresent invention. Battery charging circuitry 100 includes MOSFET 110,having a source 112 (S1) and a gate 114 (G1), and MOSFET 120, having asource 122 (S2) and a gate 124 (G1). Source 112 is connected to abattery and source 122 is connected to the device requiring the batteryor a charger or both. Control circuit 130 is connected to sources 112and 122 and gates 114 and 124. Control circuit 130 monitors sources 112and 122 and, depending on factors such as the voltage of sources 112 and122 and the state of the battery or charger. Control circuit 130 biasesgates 114 and 124 to allow the battery or charger to power the device orto allow the charger to charge the battery.

FIG. 2 shows a prior art bi-directional switch monolithic circuit suchas Siliconix's Si8900EDB and International Rectifier's FlipFET. Thesedevices typically have a substrate 110 and an epi layer 112, which, inthis example, is of n conductivity type with N+ and N majority carrierconcentrations, respectively. These are vertical trench MOSFET devicesusing a number of parallel trench MOSFETs 120 a and 120 b in p-wells 135a and 135 b. Trench MOSFETs 120 a and 120 b are controlled by gates 130a and 130 b, respectively. Current flows through sources 140 (S1) and150 (S2), which in FIG. 2 is shown as flowing from source 140, downthrough trench MOSETs 120 a, down to and across epi layer 112, and backup to source 150 through trench MOSFETS 120 b. In the prior art example,S1 and S2 are in two sections of the die, thus there is a long currentpath between S1 and S2 which constitute about 50% of the totalresistance.

FIGS. 3-6 shows different aspects of the present invention, inparticular, different MOSFETs used in the present invention. Inparticular, the MOSFET of FIG. 3 has a substrate 310 of p conductivitytype and implanted P-well 312. Formed in P-well 312 are regions 320 and330 of n conductivity type having N+ and N majority carrierconcentrations. Although wells are described in this and otherembodiments, one skilled in the art may instead use epitaxial regions oruse other methods to dope the appropriate regions with the desiredconductivity type instead of using implanted wells.

Source 340 is placed over region 320, drain 350 is placed over region330, and gate 360 is placed, with an insulating layer (e.g. SiO₂),between source 340 and drain 350. In this embodiment gate 360 overlaysthat portion of P-well 312 that is proximate to the surface under gate360. Gate 360 also partially extends over those sections of regions 320and 330 having the N majority carrier concentrations.

In operation, when gate 360 is biased, an n-channel forms under gate 360thereby permitting current to flow between source 340 and drain 350 viaregion 320, the n-channel under gate 360 (not shown) and region 330.

The MOSFET shown in FIG. 3 has the advantages of an NMOS structure, lowR_(ON) (e.g. 5-20 mΩ mm2) for 7-10V breakdown voltage, extremely lowQ_(g), and requires only 4 masks to fabricate (excluding metal layers).These are only exemplary numbers and may vary depending on the design.

The MOSFET of FIG. 4 has a substrate 410 of n or p conductivity type (Nor P majority carrier concentrations) and an implanted N-well 420.Formed in N-well 420 is p-well 430. Formed in p-well 430 and N-well 420are regions 440 and 450, which are of n conductivity type having N+ andN majority carrier concentrations.

Source 460 is placed over region 440 and drain 470 is placed over region450. Gate 480 is placed, with an insulating layer (e.g. SiO₂), betweensource 460 and drain 470. Gate 480 overlays a portion of region 440, aportion of p-well 430 that extends to the surface under gate 480, aportion of N-well 420 which also extends to the surface under gate 480,and a portion of region 450.

In operation, when gate 480 is biased, an n-channel forms under gate 480in p-well 430 that extends under gate 480 thereby permitting current toflow between source 460 and drain 470 via region 440, the n-channel (notshown) formed under gate 480 in p-well 430, N-well 420 and region 450.

The MOSFET shown in FIG. 4 has the advantage of a DMOS structure,reduced E-Field, low R_(ON) (e.g. 10-40 mΩ mm2) for 12-100V breakdownvoltage, improved safe operating area (“SOA”), and requires only 5 masks(excluding metal layers). These are only exemplary numbers and may varydepending on the design.

FIG. 5 a shows one cell of a MOSFET bi-directional switch using two ofthe MOSFET shown in FIG. 4 and formed with a common drain. Specifically,there is shown a substrate 410 of n or p conductivity type (N or Pmajority carrier concentrations) and implanted N-well 420. Formed inN-well 420 are p-wells 430 a and 430 b, respectively. Formed in p-wells430 a, 430 b and N-well 420 are regions 440 a, 440 b and 450, which areof n conductivity type having N+ and N majority carrier concentrations.Not shown are P+ regions electrically connecting source 460 a to p-well430 a and source 460 b to p-well 430 b to bring the sources and theirrespective p-wells to the same potential.

Sources 460 a and 460 b are placed over regions 440 a and 440 b,respectively. Drain 470 is placed over region 450. Gate 480 a is placed,with an insulating layer (e.g. SiO₂), between source 460 a and a drain470. Gate 480 a overlays a portion of region 440 a, a portion of p-well430 a that extends to the surface under gate 480 a, a portion of N-well420 which also extends to the surface under gate 480 a, and a portion ofregion 450. Gate 480 b is placed, with an insulating layer (e.g. SiO₂),between source 460 b and drain 470. Gate 480 b overlays a portion ofregion 440 b, a portion of p-well 430 b that extends to the surfaceunder gate 480 b, a portion of N-well 420 which also extends to thesurface under gate 480 b, and a portion of region 450. Use of drain 470is optional.

In operation, when gates 480 a and 480 b are properly biased forbi-directional use, an n-channel forms under gate 480 a in p-well 430 athat extends under gate 480 a and under gate 480 b in p-well 430 b thatextends under gate 480 b. This permits current to flow between source460 a and source 460 b via region 440 a, the n-channel (not shown)formed under gate 480 a in p-well 430 a, N-well 420 and region 450, then-channel (not shown) formed under gate 480 b in p-well 430 b, andregion 440 b. FIG. 5 a shows current flowing, for instance, from source460 a to source 460 b.

In another embodiment of FIG. 5 a, region 450 is comprised of part ofN-well 420—there is no further doping or implanting to change thecarrier concentrations beyond what it is for N-well 420. In this type ofembodiment, current flows between source 460 a and source 460 b acrossthat portion of N-well 420 near the upper surface.

FIG. 5 b shows an exemplary top view of one embodiment of thebi-directional switch cell of FIG. 5 a using the same labels to identifyanaloguous parts. As can be seen, the source, gate and drain regions inthis embodiment take the form of rectangular “fingers”. There is alsoshown shorts 510 which allow sources 460 a and 460 b to contact thep-well 430 a and 430 b, respectively. Contacts 520 are used to connectthe sources, and drain if desired, to other circuitry, other sources ordrains or to contact pads.

FIG. 5 c shows one cell of a MOSFET bi-directional switch using two ofthe MOSFET shown in FIG. 3 and formed with a common drain. Specifically,there is shown a substrate 310 of p conductivity type and implantedP-well 312. Formed in P-well 312 are regions 320 a, 320 b and 330, of nconductivity type having N+ and N majority carrier concentrations.

Sources 340 a and 340 b are placed over regions 320 a and 320 b,respectively. Drain 350 is placed over region 330. Gate 360 a is placed,with an insulating layer (e.g. SiO₂), between source 340 a and drain350. Gate 360 a overlays aportion of region 320 a, a portion of P-well312 that extends to the surface under gate 360 a, and a portion ofregion 330. Gate 360 b is placed, with an insulating layer (e.g. SiO₂),between source 340 b and drain 350. Gate 360 b overlays a portion ofregion 320 b, a portion of P-well 312 that extends to the surface undergate 360 b, and a portion of region 330. Use of drain 350 is optional.

In operation, when gates 360 a and 360 b are properly biased forbi-directional use, an n-channel forms under gate 360 a in the portionof P-well 312 that extends under gate 360 a and under gate 360 b in theportion of P-well 312 that is extends under gate 360 b. This permitscurrent to flow between source 340 a and source 340 b via region 320 a,the n-channel (not shown) formed under gate 360 a in P-well 312, region330, the n-channel (not shown) formed under gate 360 b in P-well 312,and region 320 b.

FIG. 6 shows another embodiment one cell of a MOSFET bi-directionalswitch in accordance with the present invention. In particular, the cellhas a substrate 610 of n conductivity type. Formed in substrate 610 areP-wells 620 a and 620 b. P-well 620 a has formed in it P+ region 640 a,and region 650 a of n conductivity type having N+ and N majority carrierconcentrations. P-well 620 b has formed in it P+ region 640 b, andregion 650 b of an n conductivity type having N+ and N majority carrierconcentrations.

Source 670 a is placed over P+ region 640 a and the portion of region650 a having the N+ majority carrier concentrations. Source 670 b isplaced over P+ region 640 b and the portion of region 650 b having theN+ majority carrier concentration. The P+ regions allow the sources tocontact their respective P-wells. Region 660 of n conductivity type (Nmajority carrier concentration) is formed in substrate 610. Gate 680 ais placed, with an insulating layer (eg. SiO₂), between source 670 a andgate 680 b and overlays a portion of region 650 a, P-well 620 a andregion 660. Gate 680 b is placed, with an insulating layer (e.g. SiO₂),between source 670 b and gate 680 a and overlays a portion of region 650b, P-well 620 b and region 660. Region 660 is essentially a commondrain—access to the drain is optional.

In another embodiment of FIG. 6, region 660 is comprised of part ofsubstrate 610—there is no further doping or implantating to change thecarrier concentrations beyond what it is for substrate 610. In this typeof embodiment, current flows between source 670 a and source 670 bacross that portion the substate 610 near the upper surface.

In operation, when gates 680 a and 680 b are properly biased forbi-directional use, an n-channel forms under gate 680 a in that portionof P-well 620 a that extends under gate 680 a, and an n-channel formsunder gate 680 b in that portion of P-well 620 b that extends under gate680 b. This permits current to flow between source 670 a and source 670b via region 650 a, the n-channel (not shown) formed under gate 680 a inP-well 620 a, region 660, the n-channel (not shown) formed under gate680 b in P-well 620 b, and region 650 b.

EXAMPLE 1

Referring to FIGS. 1, 5 a, 5 c and 6, there will now be discussed anexample using the present invention in a battery powered device that canbe used to charge the battery. Using the application of FIG. 1, thebi-directional switch of FIG. 5 a has sources S1 and S2 (sources 460 aand 460 b, respectively) and gates G1 and G2 (gates 480 a and 480 b,respectively). The bi-directional switch of FIG. 5 c has sources S1 andS2 (sources 340 a and 340 b, respectively) and gates G1 and G2 (gates360 a and 360 b, respectively). Likewise, the bi-directional switch ofFIG. 6 has sources S1 and S2 (sources 670 a and 670 b, respectively) andgates G1 and G2 (gates 680 a and 680 b, respectively). The battery isconnected to source S1. The device or a charger or both is connected tosource S2. Control circuit 130 is connected to sources S1 and S2 andgates G1 and G2.

If the battery has sufficient energy to drive the device, controlcircuit 130 biases gate G1 relative to source S1 and gate G2 relative tosource S2. This permits current to flow from the battery through thebi-directional switch to the device.

If the battery has insufficient energy to drive the device, forinstance, if the voltage is too low, control circuit 130 removes thebias from gate G1 thereby stopping current from flowing from S1 andisolating the battery from the rest of the device. This helps preventthe device from operating on too low a voltage which could causemalfunctions, and also prevents the battery from draining itself too lowwhich can cause damage to the battery. Gate G1 may also be closed insituations where the device is being run from the charger to preventusing the battery during such operation.

If the battery is being charged, control circuit 130 biases gate G1relative to source S1 and gate G2 relative to source S2. This permitscurrent to flow from the charger through the bi-directional switch tothe battery.

If the battery is fully charged, control circuit 130 closes gate G2 toprevent overcharging the battery, which could cause a catastrophicfailure or a fire for certain types of batteries such as lithium ionbatteries.

Table 1 compares the characteristics of certain prior art devicesagainst bi-directional switches formed with the embodiment shown inFIGS. 5 a (drain access) and 6 (no drain access)(referred to in Table 1as LateralDiscrete™): TABLE 1 R_(DSON) (typical) Rated I (A) Solder BumpDie Size Device Technology (@4.5) (Pulse/Cont) (Each FET) (mm²)Fairchild Vertical Trench 15 mΩ 20 A/9 A S = 5, D = 3, G = 1 Si: 5.2 mm²FDZ2551N Cu Carrier/BGA (3 × 6) Total: 10 mm² Siliconix Vertical Trench20 mΩ 10 A/5.4 A S = 4, D = 0, G = 1 8 mm² S18900EDB Solder Bump (2 × 5)(4 × 2 mm²) IR Vertical Trench 20 mΩ — S = 7, D = 0, G = 1 9.7 mm²FlipFET Solder Bump (4 × 4) (3.1 × 3.1 mm²) LateralDiscrete Lateral DMOS10 mΩ 10 A/5.4 A S = 7, D = 4, G = 1 6 mm² w/Drain Acess Solder Bump (6× 4) (3 × 2 mm²) LateralDiscrete Lateral DMOS 15 mΩ 10 A/5.4 A S = 7, D= 0, G = 1 4 mm² w/o DrainAcess Solder Bump (4 × 4) (2 × 2 mm²)1. A specific RDSON of 30 mΩ mm2 is assumed.2. The die sizes for LateralDiscrete are limited by the maximum currentallowed for each bump rather than RDSON requirement. A 0.5 mm pitch isassumed for solder bumps and seven (7) source bumps are used for a peakpulse current of 10 A (same as IR).As can be seen, the present invention provides a smaller on-resistancefor a given die size. It also allows the use of devices that provideaccess to the drain or devices with no access to the drain.

In accordance with another aspect of the present invention multiplecells are used to create a bi-directional switch able to handle largecurrent flows with reduced on-resistance by interleaving multiplesources and gates. This design improves the on-resistance by reducingthe current path, which reduces the on resistance, and also byconnecting the cells in parallel, which connects the resistance inparallel which also dramatically reduces the resistance. An exemplaryembodiment is shown in FIG. 7 using the cells of FIG. 5 a and using thesame labels to identify similar parts. As shown, current flows fromsources S1 (460 a) to the nearest source S2 (460 b). As will be apparentto one skilled in the art, the cells shown in FIGS. 5 c and 6 can alsobe used to create bi-directional switches using multiple cells in amanner similar to that shown in FIG. 7 with respect to the cell of FIG.5 a.

FIG. 8 shows that using multiple cells and interleaving sources andgates can also be applied to conventional technology to reduceon-resistance. In this exemplary embodiment, the prior art design ofFIG. 2 (using trench MOSFETs or planar DMOS structures) typically iscomposed of two die or areas. One die has many trench MOSFETs to createthe first source, the second die likewise has many trench MOSFETs tocreate a second source. In accordance with another aspect of the presentinvention, these large source areas are subdivided into smaller andmultiple sources S1 (140) and S2 (150) groupings and alternatelyarranged to interleave the sources and gates. This design reduces thecurrent path between sources, which reduces the on-resistance, andconnects the smaller S1 and S2 cells in parallel thereby furtherreducing on-resistance. In the exemplary embodiment, current flows fromsources S1 to the nearest source S2.

With reference to FIGS. 7 and 8, even though source S1 and S2 (and theirassociated underlying regions) are shown interleaved in a 1:1 fashionthe scoped of the invention is not limited in such a manner; sources S1and S2 may be distributed in other patterns and ratios without departingfrom the scope of the invention. Sources S1 may be dispersed amongsources S2 rather than interleaved in an interdigitated fashion.Likewise a source S1 may be associated with several sources S2 such thatcurrent flows between that source S1 and certain associated sources S2.In yet another embodiment, the current path from a source S1 to one ormore associated sources S2 is substantially similar to current pathsfrom another source S1 to its associated sources S2.

In embodiments using multiple cells (and interleaved sources and gates),multiple layers (preferably metal) are used to interconnect sources S1together, interconnect sources S2, interconnect gates G1, interconnectgates G2, and to interconnect drains if used. The performance of theseinterconnections can be improved using the novel interconnectionsdisclosed in U.S. patent application Ser. No. 10/601,121. FIG. 9 a showsa top view showing the solder bumps for a device of the presentinvention that does not provide access to the drain. FIG. 9 b shows atop view showing the solder bumps for a device of the present inventionthat provides access to the drain.

It should be apparent to those skilled in the art that the foregoing areillustrative only and not limiting, having been presented by way ofexample only. All the features disclosed in this description may bereplaced by alternative features serving the same purpose, andequivalents or similar purpose, unless expressly stated otherwise. Forinstance, one skilled in the art can reverse the conductivity typesshown in these embodiments as needed and without departing from thespirit or scope of the invention. Using FIG. 3 as an example, substrate310 and P-well 312 can be of n conductivity type, and regions 320 and330 can be of p conductivity type having P+ and P majority carrierconcentrations instead of N+ and N. Moreover, the implanted wells may bereplace by doped expitaxial layers or other methods used which impartthe same conductivity type without departing from the scope of thepresent invention. Again using FIG. 3 as an example, P-well 312 may beformed using, for instance, a doped epitaxial process rather than animplanting dopants. Therefore, numerous other embodiments of themodifications thereof are contemplated as falling within the scope ofthe present invention as defined herein and equivalents thereto.

1. A semiconductor device comprising: a. a semiconductor substratehaving an upper surface and a lower surface; b. a first region of afirst conductivity type in said semiconductor substrate and proximate tosaid upper surface; c. a first source region and a second source regionof a second conductivity type within said first region; d. a drainregion of a second conductivity type formed within said first region andproximate to said upper surface and between said first and second sourceregions; e. a first source overlaying and connecting said first sourceregion; f. a second source overlaying and connecting said second sourceregion; g. a first gate above said upper surface and placed between saidfirst source and said second source wherein said first gate overlays aportion of said first source region and said drain region; h. a secondgate above said upper surface and placed between said second source andsaid first gate wherein said second gate overlays a portion of saidsecond source region and said drain region.
 2. A semiconductor devicecomprising: a. a semiconductor substrate having an upper surface and alower surface; b. a first region of a first conductivity type in saidsemiconductor substrate and proximate to said upper surface; c. a secondregion and a third region of a second conductivity type within saidfirst well region; d. a first source region of a first conductivity typewithin said second region and a second source region having a firstconductivity type within said third region; e. a first source overlayingand connecting said first source region; f. a second source overlayingand connecting said second source region; g. a first gate above saidupper surface and placed between said first source and said secondsource wherein said first gate overlays a portion of said first sourceregion and said second region; h. a second gate above said upper surfaceand placed between said second source and said first gate wherein saidsecond gate overlays a portion of said second source region and saidthird region.
 3. A semiconductor device of claim 2 further comprising:a. a drain region of a first conductivity type formed within said firstregion and proximate to said upper surface and placed between saidsecond and third regions.
 4. A semiconductor device comprising: a. asemiconductor substrate having an upper surface and a lower surface; b.a first region and a second region of a first conductivity type in saidsemiconductor substrate and proximate to said upper surface; c. a firstconnecting region within said first region of a first conductivity typeand a first source region within said first region of a secondconductivity type; d. a second connecting region within said secondregion of a first conductivity type and a second source region withinsaid second region of a second conductivity type; e. a first sourceoverlaying and connecting said first source region; f. a second sourceoverlaying and connecting said second source region; g. a first gateabove said upper surface and placed between said first source and saidsecond source wherein said first gate overlays a portion of said firstsource region and said first region; h. a second gate above said uppersurface and placed between said second source and said first gatewherein said second gate overlays a portion of said second source regionand said second region.
 5. A semiconductor device of claim 4 furthercomprising: a. a drain region of a second conductivity type formedwithin said substrate and proximate to said upper surface and placedbetween said first and second well regions.
 6. A semiconductor devicecomprising: a. a semiconductor substrate having an upper surface and alower surface; b. a first region of a first conductivity type proximateto said upper surface; c. a plurality of second regions of a secondconductivity type within said first well region, each of said secondregion having a first source region of a first conductivity type withinsaid second regions; d. a plurality of third regions of a secondconductivity type within said first region, each of said third regionhaving a second source region of a first conductivity type within saidthird region; e. a plurality of first sources overlaying and connectingsaid plurality of said first source regions; f. a plurality of secondsources overlaying and connecting said plurality of said second sourceregions; g. a plurality of first gates above said upper surface whereineach first gate is placed between a first source and a second source andoverlays a portion of said first source region and said second region;h. a plurality of second gates above said upper surface wherein eachsecond gate is placed between a second source and first gate andoverlays a portion of said second source region and said third region.7. A semiconductor device in accordance with claim 6 further comprising:a. a plurality of drain regions of a first conductivity type and withinsaid first region wherein each drain region is between a second regionand a third region.
 8. A semiconductor device comprising: a. a pluralityof first sources; b. a plurality of second sources wherein current flowsfrom a first source to an associated second source.
 9. A semiconductordevice in accordance with claim 8 wherein said first sources aredispersed among said second sources.
 10. A semiconductor device inaccordance with claim 8 wherein current paths from different firstsources to associated second sources are substantially similar.